In silicon chip etching, a hole, or via, is machined through a substrate (die) or through multiple stacked dice to create a path for the interconnects. For some silicon chips, many holes must be etched on a very small surface. Additionally, the holes must have a high aspect ratio (deep, but not wide). Chips used in today's computing devices must combine high performance and low cost with small size. Therefore, many of these chips are packaged in stacked sets. “Through Silicon Via” (TSV) interconnection technology is used for machining these high density memory chip packages. This technique involves creating vertical connections through the stacked chips. The stacked chips are interconnected by wire bonding, which requires deep vertical gaps with a high aspect ratio. These micron-sized holes penetrate through the silicon vertically to connect circuits directly to the processor. The addition of the vertical connections creates a three-dimensional interconnect.
One of the most widely used technologies for chip etching is the dry etching process. The dry etching technology can be split into three separate classes called reactive ion etching (RIE), sputter etching, and vapor phase etching. In RIE, the substrate is placed inside a reactor in which several gases are introduced. Plasma is struck in the gas mixture using an RF power source, breaking the gas molecules into ions. The ions are accelerated towards, and react at, the surface of the material being etched, forming another gaseous material. This is known as the chemical part of reactive ion etching. There is also a physical part which is similar in nature to the sputtering deposition process. If the ions have high enough energy, they can knock atoms out of the material to be etched without a chemical reaction. It is a very complex task to develop dry etch processes that balance chemical and physical etching, since there are many parameters to adjust. By changing the balance it is possible to influence the anisotropy of the etching, since the chemical part is isotropic and the physical part highly anisotropic the combination can form sidewalls that have shapes from rounded to vertical. A schematic of a typical reactive ion etching system is shown in the figure below.
Referring to FIG. 1 there is shown an illustration of a reactive ion etching system used for etching on silicon wafers. A reactor 120 encloses the gases and plasma used in the process. In this example, there are four wafers 130 mounted on a wafer holder 160 which is also an electrode. Gas is introduced into the reactor through the tubes 190 and is blown out through the diffuser nozzles 180. The gas mixes with the plasma layer 150 sandwiched in between the wafer holder 160 and an upper electrode 140. A radio frequency (RF) signal is sent into the mechanism through an insulator 170 directed toward the plasma layer 150 which breaks the gas molecules into reactive ions The ions are accelerated towards, and react at, the surface of the wafer 130.
A special subclass of RIE which continues to grow rapidly in popularity is deep RIE (DRIE). In this process, etch depths of hundreds of microns can be achieved with almost vertical sidewalls. The primary technology is based on the so-called “Bosch process,” named after the German company Robert Bosch which filed the original patent, where two different gas compositions are alternated in the reactor. The first gas composition creates a polymer on the surface of the substrate, and the second gas composition etches the substrate. The polymer is immediately sputtered away by the physical part of the etching, but only on the horizontal surfaces and not the sidewalls. Since the polymer only dissolves very slowly in the chemical part of the etching, it builds up on the sidewalls and protects them from etching. As a result, etching aspect ratios of 50 to 1 can be achieved. In MEMS (Micro-Electrical-Mechanical Systems) technology the etched structures range in depths from 10 microns to 500 microns. The process can easily be used to etch completely through a silicon substrate, and etch rates are three to four times higher than wet etching.
Sputter etching is essentially RIE without reactive ions. The systems used are very similar in principle to sputtering deposition systems. The big difference is that substrate is now subjected to the ion bombardment instead of the material target used in sputter deposition.
Vapor phase etching is another dry etching method, which can be done with simpler equipment than what RIE requires. In this process the wafer to be etched is placed inside a chamber, in which one or more gases are introduced. The material to be etched is dissolved at the surface in a chemical reaction with the gas molecules. The two most common vapor phase etching technologies are silicon dioxide etching using hydrogen fluoride (HF) and silicon etching using xenon diflouride (XeF2), both of which are isotropic in nature. Usually, care must be taken in the design of a vapor phase process to not have bi-products form in the chemical reaction that condense on the surface and interfere with the etching process.
Dry etching is an enabling technology, which comes at a sometimes high cost. It requires expensive equipment, and the etching proceeds at a relatively slow rate. Therefore, there is a need for an etching technique that overcomes the problems in the prior art.